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Chapter 3: Design Rules and Procedures
3–11
Frequency Design Rules
If you use Clock_Derived blocks, and there is only one system clock, you must
generate an appropriate clock signal for connection to the hardware device input pins
for the derived clocks.
The Clock block defines the base clock domain, and Clock_Derived blocks define
other clock domains. DSP Builder specifies sample times in terms of the base clock
sample time. If there is no Clock block, DSP Builder uses a default base clock, with a
Simulink sample time of 1, and a hardware clock period of 20 ? s.
This feature is available across all device families that DSP Builder supports. If no
Clock block is present, the design uses a default clock pin named clock and a default
active-low reset pin named aclr .
The Signal Compiler block assigns a clock buffer and a dedicated clock-tree to
clock-signal input pin automatically to maintain minimum clock skew. If your design
contains more Clock and Clock_Derived blocks than there are clock buffers available,
non dedicated routing resources route the clock signals.
Clock Assignment
DSP Builder identifies registered DSP Builder blocks such as the Delay block and
implicitly connects the clock, clock enable, and reset signals in the VHDL design for
synthesis. When your design does not contain a Clock block, Clock_Derived block, or
PLL block, all the registered DSP Builder block clock pins connect to a single clock
domain (signal clock in VHDL).
Define clock domains by the clock source blocks: the Clock block, the Clock_Derived
block and the PLL block.
The Clock block defines the base clock domain. You can specify its Simulink sample
time and hardware clock period directly. If there is no Clock block, there is a default
base clock with a Simulink sample time of 1. You can use the Clock_Derived block to
define clock domains in terms of the base clock. DSP Builder specifies the sample time
of a derived clock as a multiple and divisor of the base clock sample time.
The PLL block maps to a hardware PLL. You can use it to define multiple clock
domains with sample times specified in terms of the PLL input clock. Use the PLL
input clock either as the base clock or a derived clock.
Each clock domain has an associated reset pin. The Clock block and each of the
Clock_Derived blocks have their own reset pin, the name of which is in the block's
parameter dialog box. The clock domains of the PLL block share the reset pin of the
PLL block's input clock.
When your design contains clock source blocks, DSP Builder implicitly connects the
clock pins of all the registered blocks to the appropriate clock pin or PLL output. DSP
Builder also connects the reset pins of the registered blocks to the top-level reset port
for the block's clock domain.
DSP Builder blocks fall into the following clocking categories:
■
■
Combinational blocks—the output always changes at the same sample time slot as
the input.
Registered blocks—the output changes after a variable number of sample time
slots.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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